DIGITAL DESIGN

Requirements Gathering, feasibility study & executable specification creation.

Chip architecture and Micro-architecture Design.

RTL Development and Simulation.

IP Engineering  (New IP development & Existing IP update).

SoC Integration (Custom  &  IP-XACT based integration).

RTL sign-off (CDC, Lint &  Formal checks).         

Design Verification  ( Directed, BFM,  System Verilog  & UVM ). 

C, C++, and  VIP based SoC verification.

Gate level simulation.

Low Power Verification (UPF).

ASIC/SoC Emulation. 

FPGA Prototyping of ASIC/SOC.  

RTL Synthesis & Constraints creation.

DFT (Scan, ATPG, MBIST, JTAG).

Floor-planning - Place & Route.

STA and Timing Closure. 

IR-drop Analysis & SI Closure. 

Physical Verification (DRC, LVS).

Post  Silicon Validation ( Chip bring-up,  protocols  compliance testing ).

Electrical Characterization.